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MT9041B
T1/E1 System Synchronizer
Features
* Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals Provides C1.5, C2, C3, C4, C8 and C16 output clock signals Provides 3 different styles of 8 KHz framing pulses Attenuates wander from 1.9 Hz
DS5059 ISSUE 4 June 2000
Ordering Information MT9041BP 28 Pin PLCC -40 to +85 C
* * * * *
Description
The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9041B is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, Stratum 4, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these specifications.
Applications
* * Synchronization and timing control for multitrunk T1 and E1 systems ST-BUS clock and frame pulse sources
VDD
VSS
OSCi
OSCo
C1.5o REF Phase Detector Loop Filter DCO Output Interface Circuit C3o C2o C4o C8o C16o F0o F8o F16o
Mode Select
Divider
MS
RST
FS1
FS2
Figure 1 - Functional Block Diagram
1
MT9041B
IC0 VSS RST FS1 FS2
25 24 23 22 21 20 19
VDD OSCo OSCi F16o F0o F8o C1.5o
5 6 7 8 9 10 11
REF NC
4
3 2 1 28 27 26
MT9041B
IC0 IC0 MS IC0 IC0 IC1 IC0
12 13 14 15 16 17 18
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 Name VSS IC0 NC REF VDD OSCo Ground. 0 Volts. Internal Connect. Connect to Vss No Connect. Connect to Vss Reference (TTL Input). PLL reference clock. Positive Supply Voltage. +5VDC nominal. Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi, see Figure 6. For clock oscillator operation, this pin is left unconnected, see Figure 5. Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is connected to a clock source, see Figure 5. Frame Pulse ST-BUS 16.384Mb/s (CMOS Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 16.384Mb/s. See Figure 11. Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 11. Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS operation at 8.192Mb/s. See Figure 11. Clock 1.544MHz (CMOS Output). This output is used in T1 applications. Clock 3.088MHz (CMOS Output). This optional output is used in T1 applications. Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s. Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. Ground. 0 Volts. Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/s. Positive Supply Voltage. +5VDC nominal. Description
7
OSCi
8
F16o
9
F0o
10
F8o
11 12 13 14 15 16 17 18
2
C1.5o C3o C2o C4o VSS C8o C16o VDD
C3o C2o C4o VSS C8o C16o VDD
MT9041B
Pin Description (continued)
Pin # 19 20 21 22 23 Name IC0 IC1 IC0 IC0 MS Internal Connect. Connect to Vss Internal Connect. Leave open Circuit Internal Connect. Connect to Vss Internal Connect. Connect to Vss Mode/Control Select (TTL Input). This pin, determines the device's state (Normal, or Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3. Internal Connect. Connect to Vss Internal Connect. Connect to Vss Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the REF input. See Table 1. Frequency Select 1 (TTL Input). See pin description for FS2. Reset (Schmitt Input). A logic low at this input resets the MT9041B. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. The RST pin should be held low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs are at logic high. Following a reset, the input reference source and output clocks and frame pulses are phase aligned as shown in Figure 10. FS2 0 0 1 1 Figure 1 is a functional block diagram which is described in the following sections. Frequency Select MUX Circuit The MT9041B operates on the falling edges of one of three possible input reference frequencies (8kHz, 1.544MHz or 2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference input (REF). A reset (RST) must be performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and must not be used. See Table 1. The DPLL of the MT9041B consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit (see Figure 3). Phase Detector - the Phase Detector compares the primary reference signal (REF) with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz or 2.048MHz). Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125us. This
3
Description
24 25 26
IC0 IC0 FS2
27 28
FS1 RST
Functional Description
The MT9041B is a System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links.
FS1 0 1 0 1
Input Frequency Reserved 8kHz 1.544MHz 2.048MHz
Table 1 - Input Frequency Selection Digital Phase Lock Loop (DPLL)
MT9041B
REF Reference
Phase Detector
Limiter
Loop Filter
Digitally Controlled Oscillator
DPLL Reference to Output Interface Circuit
Feedback Signal from Frequency Select MUX
Control Circuit
Figure 3 - DPLL Block Diagram is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by Bellcore GR-1244-CORE Stratum 4E. Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all three reference frequency selections (8kHz, 1.544MHz or 2.048MHz). This filter ensures that the jitter transfer requirements in ETS 300 011 and AT&T TR62411 are met. Control Circuit - the Control Circuit sets the mode of the DPLL. The two possible modes are Normal and Freerun. Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop FIlter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT9041B. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source. Output Interface Circuit The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 4. The Output Interface Circuit uses two Tapped Delay Lines followed by a T1 Divider Circuit and an E1 Divider Circuit to generate the required output signals. Two tapped delay lines are used to generate a 16.384MHz and a 12.352MHz signals. The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse
4 Tapped Delay Line 16MHz
outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle. The T1 Divider Circuit uses the 12.384MHz signal to generate two clock outputs. C1.5o and C3o are generated by dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.
T1 Divider Tapped Delay Line 12MHz
C1.5o
C3o
From DPLL
E1 Divider
C2o C4o C8o C16o F0o F8o F16o
Figure 4 - Output Interface Circuit Block Diagram The frame pulse outputs (F0o, F8o, F16o) are generated directly from the C16 clock. The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o and F16o are locked to one another for all operating states, and are also locked to the selected input reference in Normal Mode. See Figures 11 and 12.
MT9041B
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g. 30pF) loads. Master Clock The MT9041B can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. Freerun Mode Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun Mode, the MT9041B provides timing and synchronization signals which are based on the master clock frequency (OSCi) only, and are not synchronized to the reference signal (REF). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32ppm output clock is required, the master clock must also be 32ppm. See Applications - Crystal and Clock Oscillator sections.
Control and Modes of Operation
The MT9041B can operate either in Normal or Freerun modes. As shown in Table 2, pin MS selects between NORMAL and FREERUN modes.
MT9041B Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, i.e. free running mode, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock), in the presence of large jitter magnitudes at various jitter frequencies applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards.
MS 0 1
Description of Operation NORMAL FREERUN Table 2 - Operating Modes
Normal Mode Normal Mode is typically used when a slave clock source synchronized to the network is required. In Normal Mode, the MT9041B provides timing (C1.5o, C2o, C3o, C4o, C8o and C16o) and frame synchronization (F0o, F8o, F16o) signals, which are synchronized to reference input (REF). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz or 2.048MHz. From a reset condition, the MT9041B will take up to 25 seconds for the output signal to be phase locked to the reference. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1.
5
MT9041B
For the MT9041B, two internal elements determine the jitter attenuation. This includes the internal 1.9Hz low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125us. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125us. The MT9041B has nine outputs with three possible input frequencies for a total of 27 possible jitter transfer functions. However, the data sheet section on AC Electrical Characteristics - Jitter Transfer specifies transfer values for only three cases, 8kHz to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to 2.048MHz. Since all outputs are derived from the same signal, these transfer values apply to all outputs. It should be noted that 1UI at 1.544MHz is 644ns, which is not equal to 1UI at 2.048MHz, which is 488ns. Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g. seconds) as shown in the following example. What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB? - A ------ 20 usually made with large input jitter signals (e.g. 75% of the specified maximum jitter tolerance). Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT9041B, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. Capture Range Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The MT9041B capture range is equal to 230ppm minus the accuracy of the master clock (OSCi). For example, a 32ppm master clock results in a capture range of 198ppm. Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the MT9041B. Phase Slope Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the MT9041B, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of mode changes. The total phase shift may accumulate up to 200ns over
OutputT1 = InputT1 x10 OutputT1 = 20 x10 - 18 -------- 20-
= 2.5UI ( T1 )
( 1UIT1 ) OutputE1 = OutputT1 x --------------------( 1UIE1 ) ( 644ns ) OutputE1 = OutputT1 x ------------------- = 3.3UI ( T1 ) ( 488ns ) Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. Since intrinsic jitter attenuation will appear jitter signals than for accurate jitter transfer is always present, jitter to be lower for small input large ones. Consequently, function measurements are
6
MT9041B
many frames. The rate of change of the 200ns phase shift is limited to a maximum phase slope of approximately 5ns/125us. This meets the Bellcore GR-1244-CORE maximum phase slope requirement of 7.6ns/125us (81ns/1.326ms). Phase Lock Time This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) synchronizer loop filter iv) synchronizer limiter Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9041B loop filter and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently, phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical Characteristics - Performance for maximum phase lock time.
Applications
This section contains MT9041B application specific details for clock and crystal operation, reset operation and power supply decoupling. Master Clock The MT9041B can use either a clock or crystal as the master timing source. In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source may be 100ppm. For applications requiring an accurate Freerun Mode, such as Bellcore GR-1244-CORE, the tolerance of the master timing source must be no greater than 32ppm. Another consideration in determining the accuracy of the master timing source is the desired capture range. The sum of the accuracy of the master timing source and the capture range of the MT9041B will always equal 230ppm. For example, if the master timing source is 100ppm, then the capture range will be 130ppm. Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. These include absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. See AC Electrical Characteristics.
MT9041B
MT9041B and Network Specifications
The MT9041B fully meets all applicable PLL requirements (intrinsic jitter, jitter tolerance, jitter transfer, frequency accuracy, capture range and phase change slope) for the following specifications. 1. Bellcore GR-1244-CORE Issue 1, June 1995 for Stratum 4 Enhanced and Stratum 4 2. AT&T TR62411 (DS1) December 1990 for Stratum 4 Enhanced and Stratum 4 3. ANSI T1.101 (DS1) February 1994 for Stratum 4 Enhanced and Stratum 4 4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access 5. TBR 4 November 1995 6. TBR 12 December 1993 7. TBR 13 January 1996 8. ITU-T I.431 March 1993
OSCi +5V
+5V 20MHz OUT GND 0.1uF
OSCo No Connection
Figure 5 - Clock Oscillator Circuit
7
MT9041B
For applications requiring 32ppm clock accuracy, the following clock oscillator module may be used.
CTS CXO-65-HG-5-C-20.0MHz Frequency: 20MHz Tolerance: 25ppm 0C to 70C Rise & Fall Time: 8ns (0.5V 4.5V 50pF) Duty Cycle: 45% to 55% Frequency: 20MHz Tolerance: As required Oscillation Mode: Fundamental Resonance Mode: Parallel Load Capacitance: 32pF Maximum Series Resistance: 35 Approximate Drive Level: 1mW e.g., CTS R1027-2BB-20.0MHZ (20ppm absolute, 6ppm 0C to 50C, 32pF, 25)
The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9041B, and the OSCo output should be left open as shown in Figure 5. Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 6.
MT9041B OSCi 20MHz 1M
Reset Circuit A simple power up reset circuit with about a 50us reset low time is shown in Figure 7. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300ns.
MT9041B +5V R 10k RST
56pF OSCo 100
39pF
3-50pF
RP 1k C 10nF
1uH
1uH inductor: may improve stability and is optional
Figure 7 - Power-Up Reset Circuit Power Supply Decoupling The MT9041B has two VDD (+5V) pins and two VSS (GND) pins. Power and decoupling capacitors should be included as shown in Figure 8.
C1 0.1uF
Figure 6 - Crystal Oscillator Circuit The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20MHz crystal specified with a 32pF load capacitance, each 1pF change in load capacitance contributes approximately 9ppm to the frequency deviation. Consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in Figure 6 may be used to compensate for capacitive effects. If accuracy is not a concern, then the trimmer may be removed, the 39pF capacitor may be increased to 56pF, and a wider tolerance crystal may be substituted. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal specification is as follows.
+
18
15 MT9041B
1 C2 0.1uF
5
Figure 8 - Power Supply Decoupling
8
+
MT9041B
MT9041B MT9074 TTIP Link 0 TRING OUT RTIP RRING LOS To Controller Interrupt E1.5o IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 1 TO 8 MUX F0i C4b F0o C4o REF RST 1k 10k 10nF + 5V FS1 FS2 MS OSCi
20MHz + 5V
CLOCK Out 20MHz 32ppm
MT9074 TTIP Links 1-7 TRING F0i C4b
RTIP RRING
E1.5o
LOS
To Controller Interrupt
Figure 9 - Multiple E1 Reference Sources with MT9041B
Multiple E1 Reference Sources with MT9041B In this example 8 E1 link framers (MT9074) are connected to a common system backplane clock using the MT9041B. Each of the extracted clocks E1.5o go to a mux which selects one of the eight input clocks as the reference to the MT9041B. The clock choice is made by a controller using the loss of signal pin LOS from the MT9074s to qualify potential references. In the event of loss of signal by one of the framers, an interrupt signals the controller to choose a different reference clock. Disturbances in the generated system backplane clocks C4b and F0b are minimized by the phase slope limitations of the MT9041B PLL. This ensures system integrity and minimizes the effect of clock switchover on downstream trunks.
9
MT9041B
Absolute Maximum Ratings* - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 4 5 Supply voltage Voltage on any pin Current on any pin Storage temperature PLCC package power dissipation Symbol VDD VPIN IPIN TST PPD -55 Min -0.3 -0.3 Max 7.0 VDD+0.3 20 125 900 Units V V mA C mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated
Characteristics 1 2 Supply voltage Operating temperature Sym VDD TA Min 4.5 -40 Typ 5.0 25 Max 5.5 85 Units V C
DC Electrical Characteristics* - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 Supply current with:OSCi = 0V OSCi = Clock TTL high-level input voltage TTL low-level input voltage CMOS high-level input voltage CMOS low-level input voltage Schmitt high-level input voltage Schmitt low-level input voltage Schmitt hysteresis voltage Input leakage current High-level output voltage Low-level output voltage Sym IDDS IDD VIH VIL VCIH VCIL VSIH VSIL VHYS IIL VOH VOL 0.4 -50 2.4V 0.4V +50 2.3 0.8 0.7VDD 0.3VDD 2.0 0.8 Min Max 0.5 60 Units mA mA V V V V V V V A V V OSCi OSCi RST RST RST VI=VDD or 0V IOH=10mA IOL=10mA Conditions/Notes Outputs unloaded Outputs unloaded
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
10
MT9041B
AC Electrical Characteristics - Performance
Characteristics 1 2 3 4 5 6 7 8 9 10 11 Output phase slope Phase lock time Output phase continuity with: mode switch to Normal mode switch to Freerun 200 200 45 ns ns us/s 1-11 1, 3-11 1-11, 24 Capture range with OSCi at: Freerun Mode accuracy with OSCi at: 0ppm 32ppm 100ppm 0ppm 32ppm 100ppm Sym Min -0 -32 -100 -230 -198 -130 Max +0 +32 +100 +230 +198 +130 30 Units ppm ppm ppm ppm ppm ppm s Conditions/Notes 2-5 2-5 2-5 1,3-5,37 1,3-5, 37 1,3-5,37 1, 3-11
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are
with respect to ground (VSS) unless otherwise stated
Characteristics 1 2 Threshold Voltage Rise and Fall Threshold Voltage High
Sym VT VHM
Schmitt 1.5 2.3
TTL 1.5 2.0
CMOS 0.5VDD 0.7VDD
Units V V V
3 Rise and Fall Threshold Voltage Low VLM 0.8 0.8 0.3VDD * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst Chislehurst of the combination of TTL and CMOS thresholds. * See Figure 10.
Timing Reference Points ALL SIGNALS tIRF, tORF tIRF, tORF V HM VT VLM
Figure 10 - Timing Parameter Measurement Voltage Levels
11
MT9041B
AC Electrical Characteristics - Input/Output Timing
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Reference input pulse width high or low Reference input rise or fall time 8kHz reference input to F8o delay 1.544MHz reference input to F8o delay 2.048MHz reference input to F8o delay F8o to F0o delay F16o setup to C16o falling F16o hold from C16o rising F8o to C1.5o delay F8o to C3o delay F8o to C2o delay F8o to C4o delay F8o to C8o delay F8o to C16o delay C1.5o pulse width high or low C3o pulse width high or low C2o pulse width high or low C4o pulse width high or low C8o pulse width high or low C16o pulse width high or low F0o pulse width low F8o pulse width high F16o pulse width low Output clock and frame pulse rise or fall time Input Controls Setup Time Input Controls Hold Time Sym tRW tIRF tR8D tR15D tR2D tF0D tF16S tF16H tC15D tC3D tC2D tC4D tC8D tC16D tC15W tC3W tC2W tC4W tC8W tC16WL tF0WL tF8WH tF16WL tORF tS tH 100 100 -21 337 222 110 11 0 -51 -51 -13 -13 -13 -13 309 149 230 111 52 24 230 111 52 Min 100 10 6 363 238 134 35 20 -37 -37 2 2 2 2 339 175 258 133 70 35 258 133 70 9 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
See "Notes" following AC Electrical Characteristics tables.
12
MT9041B
tR8D REF 8kHz tR15D REF 1.544MHz tR2D REF 2.048MHz tRW tRW VT
VT
tRW
VT
F8o
VT
NOTES: 1. Input to output delay values are valid after a TRST or RST with no further state changes
Figure 11 - Input to Output Timing (Normal Mode)
tF8WH F8o tF0WL F0o tF16WL F16o tF16S tC16WL C16o tC8W C8o tC4W C4o tC2W C2o tC3W C3o tC15W C1.5o tC15D VT tC3W tC3D VT tC2D VT tC4W tC4D VT tC8W tC8D VT tF16H VT tF0D VT VT
tC16D
VT
Figure 12 - Output Timing 1
13
MT9041B
F8o tS MS tH
VT
VT
Figure 13 - Input Controls Setup and Hold Timing
AC Electrical Characteristics - Intrinsic Jitter Unfiltered
Characteristics 1 2 3 4 5 6 7 8 9 Intrinsic jitter at F8o (8kHz) Intrinsic jitter at F0o (8kHz) Intrinsic jitter at F16o (8kHz) Intrinsic jitter at C1.5o (1.544MHz) Intrinsic jitter at C2o (2.048MHz) Intrinsic jitter at C3o (3.088MHz) Intrinsic jitter at C4o (4.096MHz) Intrinsic jitter at C8o (8.192MHz) Intrinsic jitter at C16o (16.384MHz) Sym Min Max 0.0002 0.0002 0.0002 0.030 0.040 0.060 0.080 0.160 0.320 Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-11,18-21,25 1-11,18-21,25 1-11,18-21,25 1-11,18-21,26 1-11,18-21,27 1-11,18-21,28 1-11,18-21,29 1-11,18-21,30 1-11,18-21,33
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered
Characteristics 1 2 3 4 Intrinsic jitter (4Hz to 100kHz filter) Intrinsic jitter (10Hz to 40kHz filter) Intrinsic jitter (8kHz to 40kHz filter) Intrinsic jitter (10Hz to 8kHz filter) Sym Min Max 0.015 0.010 0.010 0.005 Units UIpp UIpp UIpp UIpp Conditions/Notes 1-11,18-21,26 1-11,18-21,26 1-11,18-21,26 1-11,18-21,26
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered
Characteristics 1 2 3 4 Intrinsic jitter (4Hz to 100kHz filter) Intrinsic jitter (10Hz to 40kHz filter) Intrinsic jitter (8kHz to 40kHz filter) Intrinsic jitter (10Hz to 8kHz filter) Sym Min Max 0.015 0.010 0.010 0.005 Units UIpp UIpp UIpp UIpp Conditions/Notes 1-11, 18-21, 27 1-11, 18-21, 27 1-11, 18-21, 27 1-11, 18-21, 27
See "Notes" following AC Electrical Characteristics tables.
14
MT9041B
AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 Jitter attenuation for 1Hz@0.01UIpp input Jitter attenuation for 1Hz@0.54UIpp input Jitter attenuation for 10Hz@0.10UIpp input Jitter attenuation for 60Hz@0.10UIpp input Jitter attenuation for 300Hz@0.10UIpp input Jitter attenuation for 3600Hz@0.005UIpp input Sym Min 0 6 12 28 42 45 Max 6 16 22 38 Units dB dB dB dB dB dB Conditions/Notes 1,3,6-11,18-19,21,25,32 1,3,6-11,18-19,21,25,32 1,3,6-11,18-19,21,25,32 1,3,6-11,18-19,21,25,32 1,3,6-11,18-19,21,25,32 1,3,6-11,18-19,21,25,32
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 7 Jitter attenuation for 1Hz@20UIpp input Jitter attenuation for 1Hz@104UIpp input Jitter attenuation for 10Hz@20UIpp input Jitter attenuation for 60Hz@20UIpp input Jitter attenuation for 300Hz@20UIpp input Jitter attenuation for 10kHz@0.3UIpp input Jitter attenuation for 100kHz@0.3UIpp input Sym Min 0 6 12 28 42 45 45 Max 6 16 22 38 Units dB dB dB dB dB dB dB Conditions/Notes 1,4,6-11,18-19,21,26,32 1,4,6-11,18-19,21,26,32 1,4,6-11,18-19,21,26,32 1,4,6-11,18-19,21,26,32 1,4,6-11,18-19,21,26,32 1,4,6-11,18-19,21,26,32 1,4,6-11,18-19,21,26,32
See "Notes" following AC Electrical Characteristics tables.
15
MT9041B
AC Electrical Characteristics - 2.048MHz Input to 2.048MHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Jitter at output for 1Hz@3.00UIpp input with 40Hz to 100kHz filter Jitter at output for 3Hz@2.33UIpp input with 40Hz to 100kHz filter Jitter at output for 5Hz@2.07UIpp input with 40Hz to 100kHz filter Jitter at output for 10Hz@1.76UIpp input with 40Hz to 100kHz filter Jitter at output for 100Hz@1.50UIpp input with 40Hz to 100kHz filter Jitter at output for 2400Hz@1.50UIpp input with 40Hz to 100kHz filter Jitter at output for 100kHz@0.20UIpp input with 40Hz to 100kHz filter Sym Min Max 2.9 0.09 1.3 0.10 0.80 0.10 0.40 0.10 0.06 0.05 0.04 0.03 0.04 0.02 Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1,5,6-11,18-19,21,27,32 1-5,6-11,18-19, 21,27,33 1,5,6-11,18-19,21,27,32 1-5,6-11,18-19,21,2733 1,5,6-11,18-19,21,27,32 1-5,6-11,18-19, 21,27,33 1,5,6-11,18-19,21,27,32 1-5,6-11,18-19, 21,27,33 1,5,6-11,18-19,21,27,32 1-5,6-11,18-19, 21,27,33 1,5,6-11,18-19,21,27,32 1-5,6-11,18-19,21,27,33 1,5,6-11,18-19,21,27,32 1-5,6-11,18-19,21,27,33
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 8kHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 3600Hz input Sym Min 0.80 0.70 0.60 0.20 0.15 0.08 0.02 0.01 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1,3,6-11,18-19,21-23,25 1,3,6-11,18-19,21-23,25 1,3,6-11,18-19,21-23,25 1,3,6-11,18-19,21-23,25 1,3,6-11,18-19,21-23,25 1,3,6-11,18-19,21-23,25 1,3,6-11,18-19,21-23,25 1,3,6-11,18-19,21-23,25
See "Notes" following AC Electrical Characteristics tables.
16
MT9041B
AC Electrical Characteristics - 1.544MHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 9 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 10kHz input Jitter tolerance for 100kHz input Sym Min 150 140 130 35 25 15 4 1 0.5 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26 1,4,6-11,18-19,21-23,26
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 2.048MHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 9 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 10kHz input Jitter tolerance for 100kHz input Sym Min 150 140 130 50 40 20 5 1 1 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27 1,5,6-11,18-19,21-23,27
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - OSCi 20MHz Master Clock Input
Characteristics 1 2 3 4 5 6 Duty cycle Rise time Fall time Frequency accuracy (20 MHz nominal) Sym Min -0 -32 -100 40 Typ 0 0 0 50 Max +0 +32 +100 60 10 10 Units ppm ppm ppm % ns ns Conditions/Notes 15,18 16,19 17,20
See "Notes" following AC Electrical Characteristics tables.
17
MT9041B
Notes:
Voltages are with respect to ground (V SS) unless otherwise stated. Supply voltage and operating temperature are as per Recommended Operating Conditions. Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels 1. Normal Mode selected. 2. Freerun Mode selected. 3. 8kHz Frequency Mode selected. 4. 1.544MHz Frequency Mode selected. 5. 2.048MHz Frequency Mode selected. 6. Master clock input OSCi at 20MHz 0ppm. 7. Master clock input OSCi at 20MHz 32ppm. 8. Master clock input OSCi at 20MHz 100ppm. 9. Selected reference input at 0ppm. 10. Selected reference input at 32ppm. 11. Selected reference input at 100ppm. 12. For Freerun Mode of 0ppm. 13. For Freerun Mode of 32ppm. 14. For Freerun Mode of 100ppm. 15. For capture range of 230ppm. 16. For capture range of 198ppm. 17. For capture range of 130ppm. 18. 25pF capacitive load. 19. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz. 20. Jitter on reference input is less than 7nspp. 21. Applied jitter is sinusoidal. 22. Minimum applied input jitter magnitude to regain synchronization. 23. Loss of synchronization is obtained at slightly higher input jitter amplitudes. 24. Within 10ms of the state, reference or input change. 25. 1UIpp = 125us for 8kHz signals. 26. 1UIpp = 648ns for 1.544MHz signals. 27. 1UIpp = 488ns for 2.048MHz signals. 28. 1UIpp = 323ns for 3.088MHz signals. 29. 1UIpp = 244ns for 4.096MHz signals. 30. 1UIpp = 122ns for 8.192MHz signals. 31. 1UIpp = 61ns for 16.384MHz signals. 32. No filter. 33. 40Hz to 100kHz bandpass filter. 34. With respect to reference input signal frequency. 35. After a RST or TRST. 36. Master clock duty cycle 40% to 60%.
18
Package Outlines
F
A G
D1 D
D2
H E E1 e: (lead coplanarity) A1 I E2 Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) For D & E add for allowable Mold Protrusion 0.010"
20-Pin
Dim
28-Pin Min
0.165 (4.20) 0.090 (2.29) 0.485 (12.32)
44-Pin Min
0.165 (4.20) 0.090 (2.29) 0.685 (17.40)
68-Pin Min
0.165 (4.20) 0.090 (2.29) 0.985 (25.02)
84-Pin Min
0.165 (4.20) 0.090 (2.29) 1.185 (30.10)
Min
A A1 D/E D1/E1 D2/E2 e F G H I
0.165 (4.20) 0.090 (2.29) 0.385 (9.78) 0.350 (8.890) 0.290 (7.37) 0 0.026 (0.661) 0.013 (0.331)
Max
0.180 (4.57) 0.120 (3.04) 0.395 (10.03)
Max
0.180 (4.57) 0.120 (3.04) 0.495 (12.57)
Max
0.180 (4.57) 0.120 (3.04) 0.695 (17.65)
Max
0.200 (5.08) 0.130 (3.30) 0.995 (25.27)
Max
0.200 (5.08) 0.130 (3.30) 1.195 (30.35)
0.356 0.450 0.456 0.650 0.656 0.950 0.958 1.150 1.158 (9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413) 0.330 (8.38) 0.004 0.032 (0.812) 0.021 (0.533) 0.390 (9.91) 0 0.026 (0.661) 0.013 (0.331) 0.430 (10.92) 0.004 0.032 (0.812) 0.021 (0.533) 0.590 (14.99) 0 0.026 (0.661) 0.013 (0.331) 0.630 (16.00) 0.004 0.032 (0.812) 0.021 (0.533) 0.890 (22.61) 0 0.026 (0.661) 0.013 (0.331) 0.930 (23.62) 0.004 0.032 (0.812) 0.021 (0.533) 1.090 (27.69) 0 0.026 (0.661) 0.013 (0.331) 1.130 (28.70) 0.004 0.032 (0.812) 0.021 (0.533)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
0.050 BSC (1.27 BSC) 0.020 (0.51)
Plastic J-Lead Chip Carrier - P-Suffix
General-10
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